Design-for-(low)-power is now a common part of the design process.
Indeed, NMI has run two events (2007, 2008) on this subject in recent years. But what about verification of a low-power design? What impact do design techniques for low-power have on the verification process?
And how can you verify a system with multiple voltage domains, any ofwhich can be powered-down independently?
This event looked at the challenges and pitfalls facing those who not only have to verify the ‘normal’ functional behaviour of a system but also handle the complexity introduced by low-power designs.
- Robin Kennedy, NMI “Welcome and Introduction”
- University of Bath, Chris Clarke “Introduction to Low-Power”
- TVS, Mike Bartley, “An Overview of the Verification Challenges Posed by Low-Power Design”
- Cadence Design Systems, Micheal Munsey “Metric Driven Low Power Verification”
- Air Semiconductor, David Tester “GPS 24/7 and Low-Power Verification – the Air Way…”
- Mentor Graphics, Nigel Elliot “A Low-Power Verification Flow Using UPF”
- ST-Ericsson, Pondori Kurade “The Implementation of Power Aware Verification on Digital SoC”
- Synopsys, Bhavesh Patel “Voltage aware Simulation and low power static checking using Mvtools”
- Analog Devices, Alan Whooley “Evaluation of low power verification techniques on a microcontroller-based SoC”
- Calypto Design Systems, Richard Langridge “Verification in a Clock Gating Based Low Power Flow”