Multi-Core & Multi-Processor systems have been gaining ground for a number of years. Now with the complexity of such systems rapidly increasing, the ending of the ‘free lunch’ delivered by successive generations of silicon technology and the need for performance gains coupled with energy efficiency, what is the way forward?
Hosted at Savoy Place, London by The National Microelectronics Institute (NMI), in collaboration with the UK’s nanoCMOS Consortium, ICCV 2009 “Living with Variability” attracted expert speakers from around the world and an international audience representing chip designers, manufacturers and tool vendors.
The National Microelectronics Institute (NMI) and TWI organisaed the fourth in a series of annual one-day seminars addressing microelectronics packaging trends, technologies and applications which was hosted at TWI, Granta Park, Great Abington, Cambridge. The 2009 seminar focused on the Microelectronics Packaging Roadmap and had been timed to coincide with the recent publication of the 2009 Global Packaging Roadmap by … Read More
he National Microelectronics Institute (NMI) and TWI organised the fourth in a series of annual one-day seminars addressing microelectronics packaging trends, technologies and applications which was hosted at TWI, Granta Park, Great Abington, Cambridge.
This event looked at the challenges, issues and opportunities in both porting existing and creating new designs in deeper sub-micron technologies, including modelling and co-simulation. Along the way, we also questioned whether it is always appropriate that analogue designs should track the digital.
This event, part of the NMI Analogue/Mixed-Signal/RF Network, looked at the technologies behind a range of high speed wireline and wireless technologies and consider the challenges in meeting the demand for ever increasing data rates. We also looked at the evolution of telecommunications networks, the opportunities created by greater integration of infrastructure and an initiative to develop the next generation of communications engineers.
This event looked at the challenges and pitfalls facing those who not only have to verify the ‘normal’ functional behaviour of a system but also handle the complexity introduced by low-power designs.