FPGA Network: “What Next After Flicking the Switch?”

GrantrMembers, Past Events

So, we’ve got that great design entered into the tools and it’s verified and passing though P&R without timing errors. Everything is running to schedule but now comes the really exciting part. We get to download our design into a live FPGA. We release Reset and hold our breath.

Now what?

There may well be as many different approaches to bringing up and debugging designs In-Lab and In-the-Field as there are FPGA design teams. Each of those approaches may use a different combination of tools on the bench and each has its own advantages, but probably also has areas that could be improved. By pooling our experiences in the NMI FPGA Network, we can each learn some new best-practises and accelerate this somewhat unpredictable stage of our FPGA projects.

We have worked with users and suppliers in the FPGA community to assemble an agenda around debug of FPGAs in system, including the embedded software and the high-speed serial IO. All of those things that can really hold up a project if not done efficiently.

Agenda

8:30 Registration

9:15 Welcome and Introduction
Doug Amos, NMI

Session 1

FPGA Debug: How Hard Can it Be?
Didier Martiny, Yugo Systems

Follow-On Discussion: What are the Best Practices in the Lab?
NMI Led Discussion

The Debug Formula – Can You Bottle Debug Skills?
Andy Culmer/Aysa Davey, ITDev

Session 2

How we Debug FPGAs in Automotive Designs
Martin Thompson, TRW Conekt

Challenges and Opportunities of Debugging Systems with SoC FPGAs
Kris Chaplin, Altera

Debug and Stimulus Techniques for FPGA-Based IP Validation
Andrew Gardner, ARM

LUNCH

Session 3

High Speed Transceiver Debugging (including live demo)
Dave Taylor, Xilinx

Debugging High-Speed PCIe and USB Links in Hardware and System Development (including live demo)
John Barnard, Telexsus

Session 4

Who’s Bug Is It? – The Elusive Systemic Error.
Alex Grove, FirstEDA

What have we Learned?
NMI Led Discussion

16:00 Event Close

If your manager has ever asked you why it is taking a while longer than expected to get that FPGA working, then this might be the right session for you.

Sponsors

Thank you to our event sponsors: