NMI would like to thank once again all those who attended the FPGA Network meet-up on “Design Tools and Methodologies”. Thank you also to our host Intel, and our Sponsors and Exhibitors Cadence, Mentor Graphics, Resource Group, Sarsen Technology and Synopsys.
Please, click here to see speakers’ biographies and presentations abstracts. To see PDF of presenters’ slide, please follow links below.
Registration & Coffee – Networking and Sponsor Table-tops
Welcome and introduction
Flexible debug and visibility techniques to enhance all FPGA design and deployment cycles
– Andy Jolley, Synopsys
FPGA platform development kit enables fast TTM
– Chad Hamilton, BittWare Inc.
Staying competitive by evolving your FPGA verification methodologies
– Alex Grove, Mentor Graphics
A game changer for VHDL verification: advanced HDL verification – made simple for anyone
– Espen Tallaksen, Bitvis AS
100M gate designs in FPGAs – fact or fiction?
– Jonathan Meadowcroft, Cadence
FPGA real-time debug with vastly increased operational capture time – live demo
– Nick Hardy, Telexsus
Zen and the art of high-speed design
– Mark Connor, ALTERA now part of Intel
Vivado HLx design methodology
– John Blaine, Xilinx
Networking Coffee, Event Close