In the second of a series of articles on Fabless Silicon Manufacture, industry veteran Paul Freeman discusses cost management in the manufacturing process and the factors determining chip units costs.
I’m going to assume that low cost is not the main value proposition of your product: I’ll assume that it addresses an existing or emerging market in a way that could be summarised as “better”. But it will have a manufacturing cost associated with it, which will be determined by choices you make in its design and the effort and money you devote to the setup and management of its manufacture. The choices you should make in these areas depend on what outcome you want. Better take care to put some effort into figuring out what you want to happen.
So what determines a chip’s unit cost? Based on experience I will propose that for this discussion we assume that Silicon, Packaging and Test contribute in the ratio 70:25:5. The actual contribution of each is determined at different times in the product’s life. Silicon costs are almost entirely defined in the design phase. Packaging costs are mainly defined there, but some cost reduction opportunities might arise later, e.g. a move from gold to copper bond wires. Test costs are partly defined by your design-for-test (DFT) choices, but the main contribution will come from how the manufacturing flow is designed.
Cost should be managed through a product’s life:
• In the early days, availability matters much more than cost.
• In its middle life, quality becomes an issue.
• In maturity, costs start to matter more.
A chip design will have inherent characteristics that determine the minimum cost achievable, given limitless time, money and people. In its design you have to choose where that minimum is set, and in manufacturing development you need to choose how close you want to get to that limit. Thus you end up choosing an OPTIMAL cost (not minimum), that fits with what your business will tolerate. Furthermore, this optimal cost will vary over time. In the early days, unit cost is swamped by development costs, so can be allowed to be quite high; availability matters much more than unit cost. In its middle life, quality becomes an issue: you only find out about serious DPPM issues when you start shipping significant volumes, so don’t push too hard on cost just yet. In maturity, cost starts to matter more: you’ve got a steady demand, and you now want to live off the profits; availability and quality are under control, cost can now be your focus.
So cost should be actively managed through a product’s life.
The influence of package design on unit cost is easy to overlook. OSATs (outsourced assembly and test) cut their margins to the bone, so cost will largely be driven by your technology choice. Package technology is not as simple as it might look, and if you get it wrong, your product availability or quality is going to suffer. But packaging is frequently considered to be a poor relation to foundry and doesn’t get the attention that it requires. It’s not always terribly interesting to product designers, as it’s mainly there to provide a mechanical shield from the elements, and connectivity to the outside world (both thermal and electrical): it doesn’t usually ADD to the functionality of your product. But if it contributes a quarter (or more) of your cost base, it surely deserves more than 1% of your attention and effort.
Test is an easy target for cost management: less commitment to unchangeability is required. Here’s a simple strategy for test cost: start high and aim low. Choose the right time to take on challenges such as an octal site probe card or a test clock frequency that’s chosen based on the DUT’s (device under test) inherent silicon speed. You don’t need to do these things in order to have something in your hands. But be careful of what you assume is achievable: multiple test sites might need a rare tester configuration, so make sure your manufacturer is aware of your plans. And be careful of risking your supply chain’s stability: a poorly evaluated test technique could go haywire when an unexpected parametric variation comes out of the fab – not great at month end or when your customer’s line is ready to receive your next shipment.
And so to yield. There are two sources of yield improvement: eliminate false fails, and reduce the defect rate of the manufacturing process. The first of these, you can have more influence over if you’ve got close control of the test process (i.e. the ATE program), but it will take effort to analyse the details of your rejects and the weaknesses of the ATE program. The second is more difficult for you to address: you need to put effort into the relationship with your foundry or OSAT: providing them with clear reporting and diagnosis of failing parts in order to allow them to focus on the physical root cause requires a lot of Test / Product / Design Engineering effort.
An often overlooked discipline associated with yield is waste management. Reducing waste is about catching failures early in the manufacturing flow, before packaging or other costs have been incurred. This challenge is almost entirely in the Test and Product Engineering domains. But be careful: sometimes it is cheaper to package the die in order to be able to detect its faults, than to pay to detect them beforehand. But then, if you get a yield dip that needs close analysis, you’ve contaminated the evidence: your die have been picked from the wafer and their original locations might now be lost; your die has been packaged: it’s now difficult to get access to. You’ve got a risk management problem as well!
So cost management in your manufacturing process is a tricky thing. Careful choices have to be made about which fights to pick and when. Do you really want to just ask for “as cheap as possible”?
Paul will be speaking at the forthcoming Silicon for Systems event at Rutherford Appleton Laboratory on September 3rd. Attendance is free to NMI members.