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The next generation of processor cores such as the latest Arm® cores continue to get larger and more complex with challenging power targets. To achieve these targets, addressing power integrity at the very end of the place & route step can result in late-stage ECOs and/or change to power grid strategy severely impacting the design schedule. In this Synopsys webinar, Synopsys experts will demonstrate a fast and easy-to-deploy Redhawk-Fusion and IC Validator in-design flow using Synopsys Fusion Compiler™ that leverages machine learning to achieve power targets on an Arm® Cortex® -A78 core in 5nm. Techniques such as Dynamic power shaping (DPS), IR aware placement, IR aware CCD, IR aware ECO, and Power grid augmentation (PGA) will be discussed.

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