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High performance digital systems are increasingly required in modern life, being used to implement a diverse range of applications. These applications impact many aspects of our lives and include Future Autonomous Vehicles, Artificial Intelligence, Machine Learning, High Performance Computing, Cloud Computing / Data Centres along with Virtual and Augmented Reality.

Depending upon the deployment and use case these applications may need to implement conflicting requirements. One common conflicting requirement for edge-based applications is the need for increased processing capability, along with a reduced power budget as the application is power constrained.

Addressing these requirements and constraints, demands a systematic approach at the architectural level where cloud or edge compute may be considerations. To considering the potential implementation technologies which can be used for the solution CPU, GPU, FPGA or SoC.

Regardless of the solution chosen, time to market is key and developers need to leverage industry standard development environments, frameworks, libraries and Intellectual Property often supplied by a third party to achieve development timescales.

This results in a complex development environment, which includes hardware and software co-development and regulatory compliance in some applications resulting in a complex verification and validation strategy.

This event will be of interest to System Architects, Electronic, Software and Chip Engineers, and Engineering Mangers working in this area and in the variety of application areas that have the requirement for increased system performance.

Download the event flyer.



09:00   Registration, Coffee & Networking

09:40   Welcome & Introduction
– Derek Boyd, TechWorks

09:50  A System IP Approach to High Performance mmWave 5G Wireless Verticals
– Ray McConnell, Blu Wireless Technology

10:20   High Performance, Energy Efficient Implementation of ARM Processors
– Alan Gibbons, Synopsys

10:50   Break, Coffee and Exhibition Area

11:20    Speedup and Parallelization Models for Energy-Efficient Many-Core Systems Using Performance Counters
– Dr Fei Xia, Newcastle University

11:50   Power-Efficient Computation through Processor & Algorithm Co-Design
– Bryan Donoghue, Cambridge Consultants

12:20   Lunch, Coffee and Exhibition Area  

13:20   Practical Usage of Configurable DSPs in High Performance Systems
– Marcus Binning, Cadence

13:50   Towards Exascale Computing: The ECOSCALE Approach
– Dr Dirk Koch, School of Computer Science, University of Manchester

14:20   Break, Coffee and Exhibition Area

14:50   High Performance Design with Stratix 10
– Mark Connor, Intel

15:20   In-Network Connected Compute with FPGAs
– Suhaib Fahmy, University of Warwick

15:50   Q&A Panel Session

16:10   Event Close


Exhibition and Sponsorship Opportunities

For more information on Exhibition and Sponsorship Opportunities, please contact Rachel Palmer.