Analogue and Mixed-Signal Designs are often best implemented in mature, well established technologies. Indeed, moving such designs to smaller geometries can be difficult and lead to an increase in the size of analogue blocks as more circuitry is required to achieve previous performance. However, there is often little choice as the drive for economic benefits through increased integration and enhanced functionality in the digital section means that the analogue portion simply has to keep in step with the digital.
This event looked at the challenges, issues and opportunities in both porting existing and creating new designs in deeper sub-micron technologies, including modelling and co-simulation. Along the way, we also questioned whether it is always appropriate that analogue designs should track the digital.
- Paul Double (session chair) “Analogue at the Bleeding Edge”
- Mirics Semiconductor, Simon Atkinson : “The economic limitations of deep sub-micron integration for Analog and Mixed signal technology”
- TES Electronic Solutions, Mark Barrett : “60 GHz: Applications and Sub-Micron IC technology”
- Mentor Graphics, Barry Byford : “Flexible Technology for Mixed-Signal SoC Verification”
- Moortec, Steve Crosher : “Mixed-Signal SoC Verification – modelling & methodologies”
- iSLI, Diarmuid O’Connell : “Addressing the Shortage of Analogue Skills”
- Intel, Richard Goldman : “Introduction to RF/MS design at Intel UK”
- Cadence, Ian Clifford : “Constraint-based Analog IC Design”
- IC Mask Design, Adrian O’Shaughnessy : “Yield and DFM in Layout at Nanometer Technologies”
- Saros, Jeremy Sonander : “Producing robust, high yielding, analog IC designs in sub-micron processes”
- Synopsys, Damian Roberts : “Interoperable PDK Libraries – OpenAccess infrastructure for deep sub-micron”
- Panel Session (chaired by Peter Saul, SaulResearch) “Mixed-Signal in Deep Sub-Micron – Why? How?”
- Ron Deane, Dialog Semiconductor
- Neil Amos, Fujitsu Microelectronics
- Jim Tomkins, X-Fab
Event Supported by :
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